CS 223 Digital Design

Number systems, Binary numbers, Logic levels, transistors, gates, Boolean expressions. Combinational logic: Boolean algebra, simplification of Boolean expressions. Logic minimization with Karnaugh maps, don't-care conditions. Introduction to System Verilog. Combinational building blocks, multiplexers, decoders, propagation delays, glitches. Verilog modeling. Sequential logic: SR latch, D-latch, D flip-flop, synchronous sequential circuits. Finite State Machine design, Moore and Mealy models, state encodings, timing of sequential circuits. Verilog modeling of sequential circuits. Signed numbers, Adders, ALU, comparators. Registers, register files. Counters, timers. High level state machines, RTL design, RAM, ROM. FPGA, programmable processors. Credit units: 4 ECTS Credit units: None, Prerequisite: CS 101.

Autumn Semester (Mehmet Baray, Muhammet Mustafa Ă–zdal)

Spring Semester (Mehmet Baray)

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